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<p>A <b>pin grid array</b> (<b>PGA</b>) is a type of <a href="Integrated_circuit_packaging" title="Integrated circuit packaging">integrated circuit packaging</a>. In a PGA, the package is square or rectangular, and the pins are arranged in a regular array on the underside of the package. The pins are commonly spaced 2.54 mm (0.1") apart,<sup id="cite_ref-Nath2017_1-0" class="reference"><a href="#cite_note-Nath2017-1"><span class="cite-bracket">[</span>1<span class="cite-bracket">]</span></a></sup> and may or may not cover the entire underside of the package.

</p><p>PGAs are often mounted on <a href="Printed_circuit_board" title="Printed circuit board">printed circuit boards</a> using the <a href="Through-hole_technology" title="Through-hole technology">through hole</a> method or inserted into a <a href="CPU_socket" title="CPU socket">socket</a>. PGAs allow for more pins per integrated circuit than older packages, such as <a href="Dual_in-line_package" title="Dual in-line package">dual in-line package</a> (DIP).

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<div class="mw-heading mw-heading2"><h2 id="Chip_mounting">Chip mounting</h2></div>

<p>The chip can be mounted either on the top or the bottom (the pinned side). Connections can be made either by <a href="Wire_bonding" title="Wire bonding">wire bonding</a> or through <a href="Flip_chip" title="Flip chip">flip chip</a> mounting. Typically, PGA packages use wire bonding when the chip is mounted on the pinned side, and flip chip construction when the chip is on the top side. Some PGA packages contain multiple dies, for example <a href="Zen_2" title="Zen 2">Zen 2</a> and <a href="Zen_3" title="Zen 3">Zen 3</a> Ryzen CPUs for the <a href="Socket_AM4" title="Socket AM4">AM4 socket</a>.

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<p>A <a href="Flip-chip" class="mw-redirect" title="Flip-chip">flip-chip</a> pin grid array (FC-PGA or FCPGA) is a form of pin grid array in which the <a href="Die_(integrated_circuit)" title="Die (integrated circuit)">die</a> faces downwards on the top of the substrate with the back of the die exposed. This allows the die to have a more direct contact with the <a href="Heatsink" class="mw-redirect" title="Heatsink">heatsink</a> or other cooling mechanism.

</p><p>FC-PGA CPUs were introduced by <a href="Intel" title="Intel">Intel</a> in 1999, for Coppermine core <a href="Pentium_III" title="Pentium III">Pentium III</a> and <a href="Celeron" title="Celeron">Celeron</a><sup id="cite_ref-2" class="reference"><a href="#cite_note-2"><span class="cite-bracket">[</span>2<span class="cite-bracket">]</span></a></sup> processors based on <a href="Socket_370" title="Socket 370">Socket 370</a>, and were produced until <a href="Intel_Socket_G3" title="Intel Socket G3">Socket G3</a> in 2013. FC-PGA processors fit into <a href="Zero_insertion_force" title="Zero insertion force">zero insertion force</a> (ZIF) <a href="CPU_socket" title="CPU socket">motherboard sockets</a>; similar packages were also used by AMD.

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<div class="mw-heading mw-heading2"><h2 id="Material">Material</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Ceramic">Ceramic</h3></div>

<p>A ceramic pin grid array (CPGA) is a type of packaging used by <a href="Integrated_circuits" class="mw-redirect" title="Integrated circuits">integrated circuits</a>. This type of packaging uses a ceramic substrate with pins arranged in a pin grid array. Some <a href="CPU" class="mw-redirect" title="CPU">CPUs</a> that use CPGA packaging are the AMD <a href="Socket_A" title="Socket A">Socket A</a> <a href="Athlon" title="Athlon">Athlons</a> and the <a href="Duron" title="Duron">Duron</a>.

</p><p>A CPGA was used by AMD for Athlon and Duron processors based on Socket A, as well as some AMD processors based on <a href="Socket_AM2" title="Socket AM2">Socket AM2</a> and <a href="Socket_AM2%2B" title="Socket AM2+">Socket AM2+</a>. While similar form factors have been used by other manufacturers, they are not officially referred to as CPGA. This type of packaging uses a <a href="Ceramic" title="Ceramic">ceramic</a> substrate with pins arranged in an array.

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<div class="gallerytext">A 1.2 GHz <a href="VIA_C3" title="VIA C3">VIA C3</a> microprocessor in a ceramic package</div>

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<div class="gallerytext">133 MHz Pentium chip in a ceramic package </div>

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<div class="mw-heading mw-heading3"><h3 id="Organic">Organic</h3></div>

<p>An organic pin grid array (OPGA) is a type of connection for <a href="Integrated_circuit" title="Integrated circuit">integrated circuits</a>, and especially <a href="Central_processing_unit" title="Central processing unit">CPUs</a>, where the <a href="Silicon" title="Silicon">silicon</a> <a href="Die_(integrated_circuit)" title="Die (integrated circuit)">die</a> is attached to a plate made out of an <a href="Organic_compound" title="Organic compound">organic</a> <a href="Plastic" title="Plastic">plastic</a> which is pierced by an array of <a href="Pin" title="Pin">pins</a> which make the requisite connections to the <a href="CPU_socket" title="CPU socket">socket</a>.

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<div class="gallerytext">The underside of a <a href="Celeron" title="Celeron">Celeron</a>-400 in a PPGA</div>

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<div class="gallerytext">An OPGA CPU. Note the brown color – many OPGA parts are colored green. The die is in the center of the device, and the four gray circles are foam spacers to relieve pressure from the die, caused by the heat sink.</div>

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<div class="mw-heading mw-heading3"><h3 id="Plastic">Plastic</h3></div>

<p>Plastic pin grid array (PPGA) packaging was used by Intel for late-model Mendocino core <a href="Celeron" title="Celeron">Celeron</a> processors based on <a href="Socket_370" title="Socket 370">Socket 370</a>.<sup id="cite_ref-ThompsonThompson2003_3-0" class="reference"><a href="#cite_note-ThompsonThompson2003-3"><span class="cite-bracket">[</span>3<span class="cite-bracket">]</span></a></sup> Some pre-Socket 8 processors also used a similar form factor, although they were not officially referred to as PPGA.

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<div class="mw-heading mw-heading2"><h2 id="Pin_layout">Pin layout</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Staggered_pin">Staggered pin</h3></div>

<p>The staggered pin grid array (SPGA) is used by Intel processors based on <a href="Socket_5" title="Socket 5">Socket 5</a> and <a href="Socket_7" title="Socket 7">Socket 7</a>. <a href="Socket_8" title="Socket 8">Socket 8</a> used a partial SPGA layout on half the processor.

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<p>It consists of two square arrays of pins, offset in both directions by half the minimum distance between pins in one of the arrays. Put differently: within a square boundary the pins form a diagonal square <a href="Lattice_(group)" title="Lattice (group)">lattice</a>. There is generally a section in the center of the package without any pins. SPGA packages are usually used by devices that require a higher pin density than what a PGA can provide, such as <a href="Microprocessor" title="Microprocessor">microprocessors</a>.

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<p>A stud grid array (SGA) is a short-pinned pin grid array chip scale package for use in <a href="Surface-mount_technology" title="Surface-mount technology">surface-mount technology</a>. The polymer stud grid array or plastic stud grid array was developed jointly by the <a href="Interuniversity_Microelectronics_Centre" class="mw-redirect" title="Interuniversity Microelectronics Centre">Interuniversity Microelectronics Centre</a> (IMEC) and Laboratory for Production Technology, <a href="Siemens_AG" class="mw-redirect" title="Siemens AG">Siemens AG</a>.<sup id="cite_ref-4" class="reference"><a href="#cite_note-4"><span class="cite-bracket">[</span>4<span class="cite-bracket">]</span></a></sup><sup id="cite_ref-5" class="reference"><a href="#cite_note-5"><span class="cite-bracket">[</span>5<span class="cite-bracket">]</span></a></sup>

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<p>The reduced pin grid array was used by the socketed mobile variants of Intel's Core i3/5/7 processors and features a reduced pin pitch of 1<span class="nowrap"> </span>mm,<sup id="cite_ref-6" class="reference"><a href="#cite_note-6"><span class="cite-bracket">[</span>6<span class="cite-bracket">]</span></a></sup> as opposed to the 1.27<span class="nowrap"> </span>mm pin pitch used by contemporary AMD processors and older Intel processors. It is used in the <a href="Socket_G1" title="Socket G1">G1</a>, <a href="Socket_G2" title="Socket G2">G2</a>, and <a href="Intel_Socket_G3" title="Intel Socket G3">G3</a> sockets.

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<ul><li><a href="Ball_grid_array" title="Ball grid array">Ball grid array</a> (BGA)</li>

<li><a href="Centered_square_number" title="Centered square number">Centered square number</a></li>

<li><a href="Chip_carrier" title="Chip carrier">Chip carrier</a> - chip packaging and package types list</li>

<li><a href="Dual_in-line_package" title="Dual in-line package">Dual in-line package</a> (DIP)</li>

<li><a href="Land_grid_array" title="Land grid array">Land grid array</a> (LGA)</li>

<li><a href="Single_in-line_package" class="mw-redirect" title="Single in-line package">Single in-line package</a> (SIP)</li>

<li><a href="Zig-zag_in-line_package" title="Zig-zag in-line package">Zig-zag in-line package</a> (ZIP)</li></ul>

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<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

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</style><cite id="CITEREFVijay_Nath2017" class="citation book cs1">Vijay Nath (24 March 2017). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=xvF5DgAAQBAJ&pg=PA304"><i>Proceedings of the International Conference on Nano-electronics, Circuits & Communication Systems</i></a>. Springer. p. 304. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-981-10-2999-8</bdi>.</cite></span>

</li>

<li id="cite_note-2"><span class="mw-cite-backlink"><b><a href="#cite_ref-2">^</a></b></span> <span class="reference-text"><cite class="citation web cs1">"Intel Releases New Design for sub-$1,000 PCs". Philippine Daily Inquirer. April 24, 2000.</cite> <span class="cs1-visible-error citation-comment"><code class="cs1-code">{{cite web}}</code>: </span><span class="cs1-visible-error citation-comment">Missing or empty <code class="cs1-code">|url=</code> (help)</span></span>

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<li id="cite_note-ThompsonThompson2003-3"><span class="mw-cite-backlink"><b><a href="#cite_ref-ThompsonThompson2003_3-0">^</a></b></span> <span class="reference-text"><cite id="CITEREFRobert_Bruce_ThompsonBarbara_Fritchman_Thompson2003" class="citation book cs1">Robert Bruce Thompson; Barbara Fritchman Thompson (24 July 2003). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=kG8LcWfruOAC&pg=PT44"><i>PC Hardware in a Nutshell: A Desktop Quick Reference</i></a>. O'Reilly Media, Inc. p. 44. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-0-596-55234-3</bdi>.</cite></span>

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<li id="cite_note-4"><span class="mw-cite-backlink"><b><a href="#cite_ref-4">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.jsits.com/bga-socket/bga_summary.htm">"BGA socket/BGA 소켓"</a>. Jsits.com<span class="reference-accessdate">. Retrieved <span class="nowrap">2015-06-05</span></span>.</cite></span>

</li>

<li id="cite_note-5"><span class="mw-cite-backlink"><b><a href="#cite_ref-5">^</a></b></span> <span class="reference-text"><a rel="nofollow" class="external text" href="http://www.atplas.com/de/index/mr_index/mr_news/mr_news_business/mr_news_business-fullpage.htm?printout=1&id=7921">link</a> <span class="languageicon">(in German)</span> <a rel="nofollow" class="external text" href="https://web.archive.org/web/20111001232205/http://www.atplas.com/de/index/mr_index/mr_news/mr_news_business/mr_news_business-fullpage.htm?printout=1&id=7921">Archived</a> October 1, 2011, at the <a href="Wayback_Machine" title="Wayback Machine">Wayback Machine</a></span>

</li>

<li id="cite_note-6"><span class="mw-cite-backlink"><b><a href="#cite_ref-6">^</a></b></span> <span class="reference-text"><cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20191209133509/http://www.molex.com/mx_upload/editorial/833/Sockets_earn_intel_validation_pr.html">"Molex Sockets for Servers, Desktops and Notebooks Earn Intel® Validation"</a>. Archived from <a rel="nofollow" class="external text" href="http://www.molex.com/mx_upload/editorial/833/Sockets_earn_intel_validation_pr.html">the original</a> on 2019-12-09<span class="reference-accessdate">. Retrieved <span class="nowrap">2016-03-15</span></span>.</cite></span>

</li>

</ol></div></div>

<div class="mw-heading mw-heading2"><h2 id="Sources">Sources</h2></div>

<ul><li><cite id="CITEREFThomas,_Andrew2010" class="citation web cs1">Thomas, Andrew (August 4, 2010). <a rel="nofollow" class="external text" href="https://www.theregister.co.uk/2000/08/04/what_the_hell/">"What the Hell is… a flip-chip?"</a>. The Register<span class="reference-accessdate">. Retrieved <span class="nowrap">December 30,</span> 2011</span>.</cite></li>

<li><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://reviews.cnet.com/soho-servers/xseries-335-xeon-dp/1707-3125_7-20584151.html">"XSERIES 335 XEON DP-2.4G 512 MB"</a>. CNET. October 26, 2002<span class="reference-accessdate">. Retrieved <span class="nowrap">December 30,</span> 2011</span>.</cite></li>

<li><cite class="citation web cs1"><a rel="nofollow" class="external text" href="http://www.topline.tv/SMT_Nomenclature.pdf">"SURFACE MOUNT NOMENCLATURE AND PACKAGING"</a> <span class="cs1-format">(PDF)</span>.</cite></li></ul>

<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

<ul><li><a rel="nofollow" class="external text" href="http://support.intel.com/support/processors/sb/CS-009863.htm">Intel CPU Processor Identification</a></li>

<li><a rel="nofollow" class="external text" href="http://www.semiconductor.net/article/196993-Ball_Grid_Arrays_the_High_Pincount_Workhorses.php">Ball Grid Arrays: the High-Pincount Workhorses</a>, John Baliga, associate editor, <i><a href="Semiconductor_International" title="Semiconductor International">Semiconductor International</a></i>, 9/1/1999</li>

<li><a rel="nofollow" class="external text" href="http://www.epp-online.de/epp/live/de/fachartikelarchiv/ha_artikel/detail/330473.html">Spot on component packaging</a>, 08/1998, <i>Elektronik, Produktion & Prüftechnik</i></li>

<li><a rel="nofollow" class="external text" href="http://sandbox.cz/~covex/nse/terminy.html">Terminology</a></li></ul>

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</style><div id="Semiconductor_packages323" style="font-size:114%;margin:0 4em"><a href="Semiconductor_package" title="Semiconductor package">Semiconductor packages</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;">Single <a href="Diode" title="Diode">diode</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;"><a href="Semiconductor_device" title="Semiconductor device">3...5-pin</a></th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="TO-3" title="TO-3">TO-3</a> (TH / Panel)</li>

<li><a href="TO-66" title="TO-66">TO-66</a> (TH / Panel)</li>

<li><a href="TO-126" title="TO-126">TO-126</a> (TH / Panel)</li>

<li>TO-202 (TH / Panel)</li>

<li><a href="TO-220" title="TO-220">TO-220</a> (TH / Panel)</li>

<li>TO-247 (TH / Panel)</li>

<li>TO-273 (Super-220) (SMT)</li>

<li>TO-274 (Super-247) (SMT)</li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;">Single row</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;">Dual row</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="Thin_small_outline_package" title="Thin small outline package">TSOP / HTSOP</a></li>

<li><a href="Thin_shrink_small_outline_package" title="Thin shrink small outline package">TSSOP / HTSSOP</a></li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;">Quad row</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;">Grid array</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

</ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;"><a href="Wafer_(electronics)" title="Wafer (electronics)">Wafer</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%;text-align:left;">Related topics</th><td class="navbox-list-with-group navbox-list navbox-even hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Electronic_packaging" title="Electronic packaging">Electronic packaging</a></li>

<li><a href="Integrated_circuit_packaging" title="Integrated circuit packaging">Integrated circuit packaging</a></li>

<li><a href="List_of_electronic_component_packaging_types" title="List of electronic component packaging types">List of electronic component packaging types</a></li>

<li><a href="Printed_circuit_board" title="Printed circuit board">Printed circuit board</a></li>

<li><a href="Surface-mount_technology" title="Surface-mount technology">Surface-mount technology</a></li>

<li><a href="Through-hole_technology" title="Through-hole technology">Through-hole technology</a></li></ul>

</div></td></tr><tr><td class="navbox-abovebelow" colspan="2"><div>It is relatively common to find packages that contain other components than their designated ones, such as diodes or <a href="Voltage_regulator" title="Voltage regulator">voltage regulators</a> in transistor packages, etc.</div></td></tr></tbody></table></div></div><div><div class="zim-footer">

This article is issued from <a class="external text" title="Last edited on 2024-11-20" href="https://en.wikipedia.org/wiki/?title=Pin_grid_array&oldid=1258603944">Wikipedia</a>. The text is available under <a class="external text" href="https://creativecommons.org/licenses/by-sa/4.0/deed.en">Creative Commons Attribution-Share Alike 4.0</a> unless otherwise noted. Additional terms may apply for the media files.

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